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Advanced Search Results For "DECISION feedback equalizers"

1 - 10 of 367 results for
 "DECISION feedback equalizers"
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Transceiver Optimization for Two-Hop AF MIMO Relay Systems With DFE Receiver and Direct Link.

Publication Type: Academic Journal

Source(s): IEEE Transactions on Communications. Jun2022, Vol. 70 Issue 6, p4134-4145. 12p.

Authors:

Abstract: In this paper, we consider precoding and receiving matrices optimization for a two-hop amplify-and-forward (AF) multiple-input multiple-output (MIMO) relay system with a decision feedback equalizer (DFE) at the destination node in the presence of the d...

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Research on Co-Channel Interference Cancellation for Underwater Acoustic MIMO Communications.

Publication Type: Academic Journal

Source(s): Remote Sensing; Oct2022, Vol. 14 Issue 19, p5049, 20p

Abstract: Copyright of Remote Sensing is the property of MDPI and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles ...

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A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS.

Publication Type: Periodical

Source(s): IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Mar2022, Vol. 69 Issue 3, p1027-1040. 14p.

Abstract: This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equal...

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Soft-Input Soft-Output Block Decision Feedback Equalization for ISI Channels.

Publication Type: Academic Journal

Source(s): IEEE Transactions on Communications. Sep2021, Vol. 69 Issue 9, p6213-6224. 12p.

Abstract: In this paper, a new class of soft-input soft-output block decision feedback equalizer (BDFE) for turbo equalization over inter-symbol interference (ISI) channels under minimum mean-square error (MMSE) criterion is proposed. First, the BDFE which emplo...

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A new approach for designing and implementing ADF equalization for 5G frequency selective channel based on two operating phases of LS and RLS algorithms.

Publication Type: Academic Journal

Source(s): Telecommunication Systems. Jul2021, Vol. 77 Issue 3, p543-562. 20p.

Authors:

Abstract: In this paper, a new approach is proposed for implementing an adaptive decision feedback equalizer (ADFE) for the 5G channel. The proposed equalizer works in two phases. In the first phase, a least-squares (LS) algorithm with a variable-length training...

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Indicator-Based Constrained Multiobjective Evolutionary Algorithms.

Publication Type: Academic Journal

Source(s): IEEE Transactions on Systems, Man & Cybernetics. Systems. Sep2021, Vol. 51 Issue 9, p5414-5426. 13p.

Abstract: Solving constrained multiobjective optimization problems (CMOPs) is a challenging task since it is necessary to optimize several conflicting objective functions and handle various constraints simultaneously. A promising way to solve CMOPs is to integra...

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A 10.4–16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD.

Publication Type: Periodical

Source(s): IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Nov2021, Vol. 68 Issue 11, p4566-4575. 10p.

Abstract: A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This...

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A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance.

Publication Type: Academic Journal

Source(s): IEEE Journal of Solid-State Circuits; Sep2022, Vol. 57 Issue 9, p2856-2867, 12p

Abstract: Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, downlo...

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A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process.

Publication Type: Academic Journal

Source(s): IEEE Journal of Solid-State Circuits; Aug2022, Vol. 57 Issue 8, p2521-2531, 11p

Abstract: Copyright of IEEE Journal of Solid-State Circuits is the property of IEEE and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, downlo...

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A 56 Gbps 4‐tap PAM‐4 direct decision feedback equaliser with negative capacitance employing dynamic CML comparators in 65‐nm CMOS.

Publication Type: Academic Journal

Source(s): Electronics Letters (Wiley-Blackwell). Aug2021, Vol. 57 Issue 18, p688-690. 3p.

Abstract: Here, a 4‐level pulse amplitude modulation direct decision feedback equaliser (DFE) with a novel dynamic current‐mode‐logic comparator (DCMLC) is presented. The DCMLC breaks the trade‐off between settling time and regeneration time in traditional CML c...

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